This invention relates to a dynamic random access memory(DRAM) cell, and more particularly to a DRAM cell having no a capacitor using a silicon-on-insulator (SOI) substrate.
FIG. 1a shows a sectional view of a conventional DRAM cell and FIG. 1b shows an equivalent circuit of the DRAM cell in FIG. 1a. The reference numeral 101 denotes an isolation film, 102 a gate electrode(word line) of a transistor Q, 103 a bit line, 104 a storage electrode of a capacitor C, 105 a dielectric of the capacitor C, 106 a plate electrode of the capacitor C, 107 an intermediate insulating layer, 109 a silicon substrate, and 110 and 111 a source and a drain regions of the transistor Q. As shown in FIG. 1a and FIG. 1b, an electrically readable and programmable DRAM cell includes one transistor Q and one capacitor C. In program, the signal "0" or "1" is programmed in the capacitor C according to the charge of electrons. In read, the signal "0" or "1" programmed in the capacitor C is read through the transistor Q.
In order to increase the integrity of DRAM, it should reduce the transistor Q as well as the capacitor C in size. The capacitance of the capacitor C depends on the size of the capacitor. The capacitance of the capacitor C is decreased with reduction of the size and therefore it can not reduce in size infinitely. In order to assuredly program the signal "0" or "1" in the capacitor C and to accurately read the signal "0" or "1" programmed in the capacitor C, the capacitor C should have the capacitance of above 20 fF(femto-farad). The reason is that it is for charges accumulated in the capacitor C to directly use in driving a sense amplifier.
In more detail, in program, the signal "1" or "0" is programmed in the capacitor C by turning on the transistor Q. In read, the charges charged in the capacitor C is discharged through the transistor by turning on the transistor Q and the discharged charges are transferred to an external sense amplifier(not shown in drawings) connected to the bit line 103 through the bit line 103. At this time, the voltage variation of the sense amplifier is produced according to an amount of the transferred charges to read the signal programmed in the capacitor C.
Because a parasitic capacitor is made in the bit line, while charges discharged from the capacitor are transferred to the sense amplifier, a portion of the charges becomes extinct. In consideration of extinction of charges through the parasitic capacitor in the bit line, the capacitor having a capacitance of beyond a selected capacity, for example above 20 fF should be required in the DRAM cell. Furthermore, in case the capacitor has a relatively low capacitance, it takes a lot of time to reach charges from the capacitor to a sense amplifier, resulting in a lowering of operation speed of the DRAM cell. So as to solve the problem, the capacitor having a capacitance of beyond a selected capacity, for example above 20 fF should be required. Therefore, so as to increase the integrity of DRAM, it is very essential to reduce the size of the capacitor with maintenance of the desired capacitance. Recently, the study on the capacitor with small size and a large capacitance is in progress. For an example, the formation technology of a 3-dimensional capacitor is proposed to enlarge an effective area of a capacitor in a relatively small chip size. However, the process for fabricating the 3-dimensional capacitor is very complicate and difficult, thereby resulting in increase in fabrication cost of DRAM cells and decrease in fabrication yield.